Honored Contributor
Honored ContributorThese you posted are not TQ warnings. You must open TQ to get the complete reports about timing analysis.
Anyway I can see in the underlying pane you have 6 "critical warnings": those are probably your real problem. Display them. I suppose they are sort of "timing not met" Running Nios at 133MHz on a CIII device can be very challenging. I don't mean it is impossible, but you must be smart in placing timing contraints and be sure to meet all of them after every recompilation. Moreover I don't think the device on the NEEK board is the fastest speed grade, so this won't help you. I suggest you start testing your design with maximum of 100MHz, which is a rather safe frequency and you should get all things working rather easily. Regarding the phase, usually you need to generate the clock feeding the external sdram clock pin with a small phase lead relative to the system clock of Nios and sdram controller. You make this with an additional pll output. The required phase lead can be derived from post fit analysis of delays of sdram signals and from sdram setup and hold specification. My rule of thumb is that 1ns phase lead is good with a 100MHz clock. Regards Cris
