Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHow much is pll_c2 clock frequency you are using to drive Nios and sdram?
Is your design fully time constrained? Do you get any warning in the TQ reports? Which clock do you use to drive the sdram clk input? Have you tuned relative phase between sdram clock and pll_c2 in order to meet setup and hold requirements?