NEEK Cyclone III edition problem

First of all you must identify if your problem is with sdram or elsewhere.

You can try running Nios code from onchip ram, so you exclude sdram timing problems and external connection. I think your fpga has enough onchip ram to fit the 20kB required by your test application.

Steps:

- add at least 32kb onchip ram with sopc builder

- change Nios properties: start and exception vectors must point to onchip ram

- generate the system

- recompile fpga

- change nios syslib properties so that code, stack, data are mapped to onchip ram

- rebuild nios application

When you are able to run the application with this modified system, you can focus on sdram. You can even use the application itself to perform some tests on sdram reading and writing data.