New ContributorHello,
I am a board designer working on a custom board with a MAX10 FPGA.
I was wondering if it is possible to input a differential LVDS clock (100MHz) with very high rise\fall times, almost like a sine-wave, to a MAX10 CLK1_P\N input?
The clock feeds an internal MAX10 PLL inside the chip.
A thorough examination of the MAX10 datasheet did not reveal any rise/fall requirements for LVDS inputs.
Tal
Regular ContributorHi Tal,
I believe there is no information available regarding the specific range of rise/fall time for the I/O pins. You will need to meet the Vid and Vicm electrical levels in the datasheet for the LVDS input, but we do not specify how long they need to maintain Vid (which would imply a rise / fall time requirement). We simply don’t provide that data.
Since the LVDS input will be driving an internal PLL. Thus, they need to make sure the LVDS clock meets our min 40% / max 60% duty cycle specifications for the PLL input clock. Refer below link:
https://www.intel.com/content/www/us/en/docs/programmable/683794/current/pll-specifications.html
Regards,
Aqid
Regular ContributorAs we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
