MAX10 LVDS sine wave clock input

Hi Tal,

I believe there is no information available regarding the specific range of rise/fall time for the I/O pins. You will need to meet the Vid and Vicm electrical levels in the datasheet for the LVDS input, but we do not specify how long they need to maintain Vid (which would imply a rise / fall time requirement). We simply don’t provide that data.

Since the LVDS input will be driving an internal PLL. Thus, they need to make sure the LVDS clock meets our min 40% / max 60% duty cycle specifications for the PLL input clock. Refer below link:

https://www.intel.com/content/www/us/en/docs/programmable/683794/current/pll-specifications.html

Regards,

Aqid