LVDS and DE0-Nano

Just a short update.

Cyclone LVDS Megafunctions is just a software SERDES, using DDR registers. You can write equivalent code in your design.

I ma trying to sue FPGA to drive a TFT screen with an FPGA, which results in 7:1 serialisation ratio. My LVDS bit clock is as high as the PLL 472.5MHz, which is not enough for the 60Hz refresh rate.

I have managed to write my own SER VHDL code. However, the limiting factor is the PLL frequency. FvM, how can I use the DDR register to doouble the frequency? I tried triggering on either clock edge but Quartus kept complaining and I couldn't compile my design. I would be very grateful if you could point me in the right direction.

Here's a LVDS receiver example using altddio_in to implement DDR input registers:

chan:
FOR I IN 0 TO N_AD_CHAN - 1 GENERATE
	lvds_rcv : altddio_in
	GENERIC MAP (
		intended_device_family => "Cyclone III",
		invert_input_clocks => "ON",
		lpm_type => "altddio_in",
		power_up_high => "OFF",
		width => 1
	)
	PORT MAP (
		datain => AD9222_D(I TO I),
		inclock => fastclock,
		dataout_h => dataout_h(I DOWNTO I),
		dataout_l => dataout_l(I DOWNTO I)
	);
	PROCESS (fastclock)
	BEGIN
      IF rising_edge(fastclock) THEN
         lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I);
		END IF;
	END PROCESS;
	PROCESS (slowclock)
	BEGIN
	   IF reset = '1' THEN
	      lvds_rx(I) <= (others => '0');
      ELSIF rising_edge(slowclock) THEN
         lvds_rx(I) <= lvds_sr(I);
		END IF;
	END PROCESS;
END GENERATE;

many thanks for the example, FvM.

LVDS is 2.5v but DE0-Nano VCCIO is 3.3v, is fine?

In theory it shouldn't work but it worked fine with the TFT panel I was using. I think those input stages on some TFT panels are quite forgiving.

I think problem is not receiver but output buffer of fpga that can not work safely with 3.3v when configured for 2.5v

There are in fact no differential I/O standard supported for 3.3V VCCIO. "can not work safely" is a different thing.