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Altera_Forum
Honored Contributor
Honored ContributorLVDS and DE0-Nano
Hi, I need to use LVDS on the NE0-Nano development kit, and I have a questions with respect to how to go about it. From what I understand, I have two options: LVDS megafunction Par...
Altera_ForumHonored Contributor
Honored ContributorI ma trying to sue FPGA to drive a TFT screen with an FPGA, which results in 7:1 serialisation ratio. My LVDS bit clock is as high as the PLL 472.5MHz, which is not enough for the 60Hz refresh rate.
I was hoping megafunction would allow me to get over that obstacle, but I cannot sense the internal clock that achieves the desired data rate of 583Mbps.
