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Altera_Forum's avatar
Altera_Forum
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14 years ago

LVDS and DE0-Nano

Hi, I need to use LVDS on the NE0-Nano development kit, and I have a questions with respect to how to go about it. From what I understand, I have two options: LVDS megafunction Par...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have managed to write my own SER VHDL code. However, the limiting factor is the PLL frequency. FvM, how can I use the DDR register to doouble the frequency? I tried triggering on either clock edge but Quartus kept complaining and I couldn't compile my design. I would be very grateful if you could point me in the right direction.