Is there any option to generate 100MHZ clock without PLL in max10 device

Hi,
the linked CLKIN table is only half the story. PLL inclk can be driven directly by associated CLKIN pins or through GLCK network to allow PLL cascading and driving from other dedicated CLKIN pins. The connection option isn't explicitely shown in MAX10 device handbook PLL schematic (Figure 2-7: MAX 10 PLL High-Level Block Diagram) but mentioned in Global Clock Control Block paragraph

"The output from the clock control block in turn feeds the corresponding GCLK. The GCLK can drive the PLL input if the clock control block inputs are outputs of another PLL or dedicated clock input pins. Normal I/O pins cannot drive the PLL input clock port."

As Cyclone III, IV, 10 and MAX 10 share the same PLL architecture, you can refer to respective Cyclone 10 PLL figure if you want to see GLCK connection.

All documents correspond on PLL inclk can't be driven from other sources than dedicated CLKIN or other PLL.

Obvious question, why is it so? How does GCLK "know" if it's driven by CLKIN or other pin?

My understanding, of course it doesn't. The constraint isn't imposed by routing resources but intentionally set in the fitter. Because it's not guaranteed that free inclk routing will achieve sufficient PLL performance. It might even cause lock failure.

I suppose, Quartus has an undocumented option to allow pll inclk from other pins.

Best regards
Frank