I would like to build a connection between my master device and max v, so I program an i2c interface logic to max v which I download from opencores. But I can read from my master device but can't write correctly to the MAX V cpld.

Hi el.ign,

Thanks for your reply! The link to the documentation of the project from opencores is https://github.com/mpDean9939/I2C-MasterSlave-Verilog​.

And I have tried the "an494 example design implementing GPIO expansion using I2C bus interface on Max series", it works well but it only have slave address matching and data while no register address. So I tried to modify it's .v file but it failed in connection between my master device and max v cpld. The situation is as I asked in intel forums, the link is https://forums.intel.com/s/question/0D50P00004Mh74YSAR/failure-of-modification-to-altera-example-an494-with-register-adddress. I also attach the modified verilog file and insert the image about the instance in the top module in this chat since there must be only one attachment, so the original .v file of an494 can't be attached, you can see it via the former link.

Please help me about my problem.

Best Regards,

Liam

Thanks for your advice. But the an486 example set the MAX FPGA to a master not a slave, and I just set my MAX V to a I2C slave. So could you please help me review my I2C_to_GPIO_modify file?