New ContributorHi All,
Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks
Please see the following picture.
Regular ContributorHi,
Do you have any new update?
Regular ContributorHi,
I hope you have update for this week. Let me know.
New ContributorHi,
Sorry, I still can't get the right confiuration for simulation.
Regular ContributorHi,
Let me try and have the working config changes and upload to you and you check again from your side.
Regular ContributorHi,
I am still getting the files ready on my side.
New ContributorHi,
First of all, I want to make it clear, use for FPGA board is Ok, but for simulation, HPS used Mentor VIP.
Are you see in synth or sim directory？ At the same time, "HPS to FPGA AXI-4 Master interface" Enable/Data width : 256-bit, then you can compare the file for synth and sim directory, the synth directory is S2F_DATA_WIDTH mismatch with sim directory. "HPS to FPGA AXI-4 Master interface" Enable/Data width : 128-bit, The compare data width is Match.
Then I found other question, as following.
AXI4 Don't support AXI_USE_WUSER.
Regular ContributorHi,
I only check the files are reflected in the synth folder every time I changed the settings, let me compare them now then for sim.
Regular ContributorHi,
I just got back to this issue, and testing your observation on the GHRD, I share the result to you once ready.
Regular ContributorHi,
I have tested multiple tests, using the GHRD on Quartus 22.2, after Upgrading the IP, I am able to see the changes correctly for both synth and sim, and for all settings.
Could you try using the GHRD?:
Regular ContributorHi,
Do you have any update?
Could you try using the GHRD? The link is in my previous comment.
New ContributorHi.
I will try that.
