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yu1987-08-22's avatar
yu1987-08-22
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3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
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2 years ago

Hi,


I am still getting the files ready on my side.


  • yu1987-08-22's avatar
    yu1987-08-22
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    2 years ago

    Hi,

    First of all, I want to make it clear, use for FPGA board is Ok, but for simulation, HPS used Mentor VIP.

    Are you see in synth or sim directory？ At the same time, "HPS to FPGA AXI-4 Master interface" Enable/Data width : 256-bit, then you can compare the file for synth and sim directory, the synth directory is S2F_DATA_WIDTH mismatch with sim directory. "HPS to FPGA AXI-4 Master interface" Enable/Data width : 128-bit, The compare data width is Match.

    Then I found other question, as following.

    AXI4 Don't support AXI_USE_WUSER.