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yu1987-08-22's avatar
yu1987-08-22
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3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All,

Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks

Please see the following picture.

36 Replies

  • Hi,

    I try that, found that, different with us. Should use plantform gerenate new HPS.

  • Hi,


    Did you try to change the settings you mentioned previously just to check if the sim & synth files are in sync when changes all the settings in Platform Designer?


  • Hi,

    Thanks for your help. I ask FAE, he found the question, and update for me the new Quartus version about 23.2 will solved this question.

  • Hi,


    Thanks for the info, I have seen the case and the fix will be in Quartus 23.2, we apologies for any inconvenience in our support we appreciate your feedback.


    If no further related questions, could we close the thread?


  • Hi,


    I hope that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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