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yu1987-08-22's avatar
yu1987-08-22
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3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
yu1987-08-22's avatar
yu1987-08-22
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3 years ago

Hi,

Thanks for your help. I ask FAE, he found the question, and update for me the new Quartus version about 23.2 will solved this question.