Forum Discussion
yu1987-08-22
New Contributor
New ContributorHPS(Hard Process system) generate Verilog for Simulation
Hi All,
Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks
Please see the following picture.
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EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Did you try to change the settings you mentioned previously just to check if the sim & synth files are in sync when changes all the settings in Platform Designer?
