Forum Discussion
yu1987-08-22
New Contributor
New ContributorHPS(Hard Process system) generate Verilog for Simulation
Hi All,
Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks
Please see the following picture.
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EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
I have tested multiple tests, using the GHRD on Quartus 22.2, after Upgrading the IP, I am able to see the changes correctly for both synth and sim, and for all settings.
Could you try using the GHRD?:
