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yu1987-08-22

New Contributor

3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...

EBERLAZARE_I_Intel

Regular Contributor

2 years ago

Hi,

I have tested multiple tests, using the GHRD on Quartus 22.2, after Upgrading the IP, I am able to see the changes correctly for both synth and sim, and for all settings.

Could you try using the GHRD?:

https://releases.rocketboards.org/2021.11/gsrd/agilex_gsrd/agilex_soc_devkit_ghrd_enpirion_QPDS-21.3pro-21.1std.tar.gz

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HPS(Hard Process system) generate Verilog for Simulation

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