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yu1987-08-22's avatar
yu1987-08-22
Icon for New Contributor rankNew Contributor
3 years ago

HPS(Hard Process system) generate Verilog for Simulation

Hi All, Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks Please see the following picture. ...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


I just got back to this issue, and testing your observation on the GHRD, I share the result to you once ready.