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2258432's avatar
2258432
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

How to use AvalonMM-AvalonMM mode of mSGDMA

Hello, I want to use mSGDMA to move data from the FPGA side to HPS DDR3. I referred to writing_to_hps_memory and used the same design to complete the data movement process. My data width is 32 bit...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,

I think the FIFO out port address is a secure memory regions for a slave. It's can be interpreted like in Platform Designer User Guide.

  • 2258432's avatar
    2258432
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello Adzim,

    Thanks for your reply. I think you are right. I tried not specifying the address for reading data, but only the address for writing data, and the result was that the data could be moved to HPS DDR3 normally.

    However, I have another issue. When my data is 32-bit, I use AvalonST-AvalonMM mode mSGDMA dispatcher, and my write master parameter is set as shown in the following image.

    I tried to change the Maximum Burst Count to 32, but when executing the program on the HPS side, mSGDMA did not write data to HPS DDR3, and HPS was unable to operate and had to restart.

    When data is 16 bits, I use the AvalonMM-AvalonMM mode mSGDMA dispatcher, while the Length Width and Maximum Burst Count of the read/write master can only be set to 16 and 8. Setting other values will also result in HPS side failure to operate.

    I would like to know what the Length Width parameter of the read/write master refers to? I couldn't find an explanation for this in the official documents.