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iiwan's avatar
iiwan
Icon for New Contributor rankNew Contributor
5 years ago

How to tell quartus for multiple clock

I have part of my disign for Stratix V, that works on rx_std_clkout and tx_std_clkout from Transceiver Native PHY IP core, and dynamically change speed via Transceiver Reconfigurator IP core. I use word aligner, 8b/10b codec, byte ordering. 40 bit bus. But I think, that quartus not compile my design well, and how can I tell, that I want to work on different speed?

8 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Just to ensure we are on the same page, would you mind to further elaborate on the "quartus not compile design well" observation? Just wonder if you are referring to timing constraining your design which will be working on different speed?


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin



    • iiwan's avatar
      iiwan
      Icon for New Contributor rankNew Contributor
      5 years ago
      No, I mean, that, at start speed of Native Phy speed 2,5Gb and rx and tx clkout has freq 62,5 Mhz, than I dynamically reconfigure to 5Gb and 10Gb, so my tx and rx clkout has 125 and 250 Mhz. But I think, Quartus compile good only for 62,5 Mhz, and when I change speed, it works not good as I expected. So question is, how to tell Quartus in my project, that my modules have to work good at every clk, 62,5 , 125, 250 Mhz.

      P.S. I think, if I set at beginning speed 10Gb and then downgrade to 2,5Gb, its not good idea too.
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. Yes, you are right, when you perform dynamic reconfiguration, the tx/rx_clkout frequency will change according to your new XCVR data rate.


    Would you mind to further elaborate on what is referred by "it works not good as I expected"? For example, do you observe your core logic behave incorrectly?


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin



    • iiwan's avatar
      iiwan
      Icon for New Contributor rankNew Contributor
      5 years ago
      Yes, my core logic not working well. After dynamic reconfiguration to 5Gbps(125Mhz) my logic approx in 80 % of case work good, but to 10Gbps(250Mhz) not working at all.

      P.S. For example can you tell how to make sdc file to tell, that my modules have to work at 3 freq, like Ethernet Triple(1, 2,5 and 10G) speed. Or I have to do something another way?
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. Regarding your specific inquiry on setting the right SDC constraints so that Timing Analysis can take care of different core frequencies, we will need to further engage our Timing Team on this. Since I am unable to open a Forum case on your behalf, would you mind to open a new Forum case on this and let me know the case number. I will help to route to Timing Team for further support.


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin



  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your help. I have notified the timing team to expedite the routing of the new Forum case.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    For your information, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.