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iiwan's avatar
iiwan
Icon for New Contributor rankNew Contributor
5 years ago

How to tell quartus for multiple clock

I have part of my disign for Stratix V, that works on rx_std_clkout and tx_std_clkout from Transceiver Native PHY IP core, and dynamically change speed via Transceiver Reconfigurator IP core. I use w...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. Regarding your specific inquiry on setting the right SDC constraints so that Timing Analysis can take care of different core frequencies, we will need to further engage our Timing Team on this. Since I am unable to open a Forum case on your behalf, would you mind to open a new Forum case on this and let me know the case number. I will help to route to Timing Team for further support.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin