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iiwan's avatar
iiwan
Icon for New Contributor rankNew Contributor
5 years ago

How to tell quartus for multiple clock

I have part of my disign for Stratix V, that works on rx_std_clkout and tx_std_clkout from Transceiver Native PHY IP core, and dynamically change speed via Transceiver Reconfigurator IP core. I use w...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Thanks for your update. Yes, you are right, when you perform dynamic reconfiguration, the tx/rx_clkout frequency will change according to your new XCVR data rate.


Would you mind to further elaborate on what is referred by "it works not good as I expected"? For example, do you observe your core logic behave incorrectly?


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



iiwan's avatar
iiwan
Icon for New Contributor rankNew Contributor
5 years ago
Yes, my core logic not working well. After dynamic reconfiguration to 5Gbps(125Mhz) my logic approx in 80 % of case work good, but to 10Gbps(250Mhz) not working at all.

P.S. For example can you tell how to make sdc file to tell, that my modules have to work at 3 freq, like Ethernet Triple(1, 2,5 and 10G) speed. Or I have to do something another way?