How to Read/Write L4 Peripheral Slave Bus on S10 SX Device

Hello All，

I meet a problem about reading/writing L4 Peripheral Slave Bus on S10 SX Device.

I code avalon_mm_read_master module and avalon_mm_write_master module by myself, and I put them into Platform Designer as Figure 1 shown.

I firstly set the read and write address to DDR address such as 0x7fff0000. Data grabed in SignalTap shows read and write succeed.

 

Then I change read and write address to l4 slave peripheral address such as uart(0xffc02000) and gpio(0xffc03000). Data grabed in SignalTap shows in Figure 2 and Figure 3. From figures, the operation that data is written into the exact setting address succeeds, but data read out of the address is all zero, which means data cannot be read/wrote into l4 slave peripheral bus address.

 

The tools version all I use are 19.1 Pro Quartus Prime, 2017.09 uboot, 4.9.78-ltsi-altera linux, S10 device number is 1sx280lu2f50e2vgs2(Stratix 10 SoC Development Kit, ES Edition).

What I do is I use sdimage in https://releases.rocketboards.org/release/2019.04/gsrd/s10_gsrd/ and I change dtb file which add uart1 with status "okay", also I change the u-boot.scr file like https://rocketboards.org/foswiki/Documentation/S10SGMIIRDV181CreateUbootScript and extra configure some firewall registers of l4 slave peripheral bus. The u-boot.scr is also attached below.

Could you please give me some suggestions what I can do?

Thank you very much!