How to make clk and loaden of external PLL for altlvds on cylone 10?

Question

Hi everyone,

When I use Arria V to implement high-speed lvds output, I use altlvds ip with external Pll, I need altera_pll_lvds_output to make clk and loaden outputed from external pll as lvds signal for the clk and load of altlvds? But when I use Cyclone 10, which primitive I need like altera_pll_lvds_output?

Best regards,

lambert

lambert · Answer

Because now the lvds serdes module has integrated lvds clock tree.​

rahul_s_intel1 · Answer

In Cyclone 10 GX , the serdes is using altera lvds ip not alt lvds iphttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

Forum Discussion

How to make clk and loaden of external PLL for altlvds on cylone 10?

2 Replies

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA