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Lambert
Occasional Contributor
Occasional ContributorHow to make clk and loaden of external PLL for altlvds on cylone 10?
Hi everyone, When I use Arria V to implement high-speed lvds output, I use altlvds ip with external Pll, I need altera_pll_lvds_output to make clk and loaden outputed from external pll as lvds si...
LambertOccasional Contributor
Occasional ContributorBecause now the lvds serdes module has integrated lvds clock tree.
