New ContributorWe are using 5AGXMB1G4F40C5G with 48 bit(x16 - 4 Nos) DDR3L memory interface and 8/6 bit ECC. We planned to use DDR3 controller in Soft IP. There are only 5 DQS pairs are available in pinout but DDR3 memory needs 8 DQS pairs. How to connect these DQS pairs?
ContributorAre you using Quartus to help determine your pinout?
If you've run out of pins then I suspect you're trying a DDR3 configuration that the FPGA won't support. There are frequently extra pins, that can be used for data or dqs signals, to offer extra flexibility in your pinout.
Put a Quartus project together, instantiating the memory interface you require, and confirm a valid pinout before going too far.
Cheers,
Alex
New ContributorHi Alex
Thanks for the response.
How does this FPGA supports DDR3 interface(Data width and Max. Memory size)?
Regards
Srikanth Kacchu
Super ContributorWhy do you need 8 DQS if you're only doing 4, x16 plus ECC? And where are you seeing that only 5 are available? Pin Planner?
You may also want to check the EMIF spec estimator:
#iwork4intel
New ContributorTotally, we are storing 45 bits of data and 8/6 bits of ECC. We are using x16 DDR3L memory devices(4 Nos).
In first DDR3L - D0 to D15 data
In second DDR3L - D16 to D31 data
In third DDR3L - D32 to D44 data
In fourth DRR3L - 8 or 6 bits of ECC
Each DDR3L memory devices has 2 DQS pairs. Since we are using 4 Nos of DDR3L devices, we need 7 to 8 DQS pairs.
We have seen the "Pin information for the Arria V 5AGXMB1 Device" document. It shows only 5 pairs of DQS signals i.e, DQS6T, DQS7T, DQS8T, DQS9T and DQS10T in x16/x18 column.
Frequent ContributorIn this case , mean the device unable to support that 45bits interface. The device only can support up to X8 *5 which is X40bits interface.
Frequent ContributorThe table in this document will tell you your device have how many x8 DQS group.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_5v2.pdf#page=235
But @a_x_h_75 is true. No matter how, you still need to make sure you can fit it using Quartus.
