New Contributor
Super ContributorWhy do you need 8 DQS if you're only doing 4, x16 plus ECC? And where are you seeing that only 5 are available? Pin Planner?
You may also want to check the EMIF spec estimator:
#iwork4intel
New ContributorTotally, we are storing 45 bits of data and 8/6 bits of ECC. We are using x16 DDR3L memory devices(4 Nos).
In first DDR3L - D0 to D15 data
In second DDR3L - D16 to D31 data
In third DDR3L - D32 to D44 data
In fourth DRR3L - 8 or 6 bits of ECC
Each DDR3L memory devices has 2 DQS pairs. Since we are using 4 Nos of DDR3L devices, we need 7 to 8 DQS pairs.
We have seen the "Pin information for the Arria V 5AGXMB1 Device" document. It shows only 5 pairs of DQS signals i.e, DQS6T, DQS7T, DQS8T, DQS9T and DQS10T in x16/x18 column.
Frequent ContributorIn this case , mean the device unable to support that 45bits interface. The device only can support up to X8 *5 which is X40bits interface.
New Contributorwith how many ECC bits?
Frequent ContributorECC also use the same DQS group of the device. So is 40bits included ECC.
