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SKacc's avatar
SKacc
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6 years ago

How to connect these DQS pairs when there is a mismatch?

We are using 5AGXMB1G4F40C5G with 48 bit(x16 - 4 Nos) DDR3L memory interface and 8/6 bit ECC. We planned to use DDR3 controller in Soft IP. There are only 5 DQS pairs are available in pinout but DDR...
a_x_h_75's avatar
a_x_h_75
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6 years ago

Are you using Quartus to help determine your pinout?

If you've run out of pins then I suspect you're trying a DDR3 configuration that the FPGA won't support. There are frequently extra pins, that can be used for data or dqs signals, to offer extra flexibility in your pinout.

Put a Quartus project together, instantiating the memory interface you require, and confirm a valid pinout before going too far.

Cheers,

Alex

SKacc's avatar
SKacc
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6 years ago

Hi Alex

Thanks for the response.

How does this FPGA supports DDR3 interface(Data width and Max. Memory size)?

Regards

Srikanth Kacchu