Help required on Ethernet with FPGA

This seems to be a recurring theme. People are wanting something simpler than the ethernet example that Altera is offering.

I really think that the Simple Socket Server example is the quickest and easiest way for you to get ethernet running. What part of it specifically is making you hesitate?

As an alternative to the TSE MAC, I would recommend using the "Avalon OpenCores MAC".

http://www.alteraforum.com/forum/showthread.php?t=3665

And not just because I made the port. It's one single drop-in component vs. the 4-5 required for the TSE MAC. It's easier to use. And it should drop right in and work with the Simple Socket Server example.

One thing I would like to do when I get a little time, is create a simpler more useful ethernet example design for hardware engineers. Something that would allow them to usefully interface with hardware. But until I get the time to do it, I recommend starting with the simple socket server. The other thing people are asking for is a patch to allow them to run the InterNiche stack without uC/OSII. Again, when I get the time.

Jake

Hi...

Where could I get the PHY address of DP83848C PHY of Nios Embeeded Eval Kit?

I couldnt get in the document given?

Hi...:)

I dont mean the MAC address..

I want to write a data to PHY.. Before the Core writes data to the Phy, the data register need to be set to the desired data and the control register must be configured with the Phy Address, Register Number and read or write option. This is how my Mii Control register looks. How should I give for the PHY? (We use Custom MAC)

mii-core control register (regbase + 16) (write)

Bit 15 -> 0

Bit 14 -> 1

Bit 13 & 12 -> 10 for Read and 01 for Write

Bits[11..7] -> PHY addr [4..0]

Bits[6..2] -> register no[4..0]

Bit 1 -> 0 for write, 1 for read

Bit 0 -> 0

I guess that you must be able to find it on the schematic of the board. Most PHYs have pins that must either be connected to ground or vcc to code the address.

The other way is to add some code in your driver to guess the PHY address. The TSE Mac driver for Interniche does that. basically it tries every address until it gets an answer.

Hi jakobjones,

I had compiled the design from http://www.alteraforum.com/forum/showthread.php?t=3665 which did not show me any errors. But after compilation when i look into the pin planner i have ceratin signals marked unknown in the direction field.

E.g

Node Name : top_hsmc_clk

Direction : unknown

Location : Pin_A1.

Similarly there are a lot number of signals having direction unknown.

Are these signals required for me to communicate with the HSMC daughter board?

Will my ethernet port work with these signals unassigned?

With these signals marked unknown will i be able to send and receive an ethernet packet?

At present i'm interested in only configuring the PHY to send and receive data.

Thanks & Regards,

Renu.

Signals with an 'unknown' direction are usually signals that have some assignments (such as location in the pin planner, i/o voltage...) but that don't exist in the top level design.

You should check for each one of them if it's a pin that you need in your design or not. If you don't need it, you can either remove the assignments (only possible in the assignment editor IIRC) or create a port for it on your top level design (and give it a default value if it's an output).

Hi,

I am working on NEEK Board. Does my ethernet port(PHY) need clock to send and receive packets or is already connected by default.

Hi Daixiwen,

I am actually using the RMII mode of my PHY which actually does not need Transmit and receive clocks. My query now is does my hsmc board of NEEK need clock or does it get the clock on board start up. That is to use the components in the hsmc board like VGA, RS232 should i assign any clocks in my top level design.

Am i not clear in my question?