Help required on Ethernet with FPGA

Signals with an 'unknown' direction are usually signals that have some assignments (such as location in the pin planner, i/o voltage...) but that don't exist in the top level design.

You should check for each one of them if it's a pin that you need in your design or not. If you don't need it, you can either remove the assignments (only possible in the assignment editor IIRC) or create a port for it on your top level design (and give it a default value if it's an output).