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Altera_Forum
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16 years ago

Getting multiple fan-out errors when compiling a scratch Nios with DDR SDRAM support

Hi,

I'm new to FPGA, working with the Altera CIII Dev Kit. I've created a base Nios system running from on-chip mem, successfully controlling pio's via SW.

Now I went to add DDR SDRAM support, did it with SOPC builder (DDR SDRAM High Performance ....). I assigned the outputs correctly, as described in the Dev Kit ref. manual.

Now when I compile the system, I get a whole bunch of these errors:

Error: The DDIO_OUT WYSIWYG primitive "my_nios:inst5|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|dq_ddio_dataout[0]" feeding the node "my_nios:inst5|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_dp_io:dpio|dqs_group[0].dq[0].dq_obuf" has multiple fan-outs

Can anybody help me out?

Best,

Erik

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi again,

    Turned out that I was using the term 'correctly' a bit cassually!

    The error came from the fact that I had assigned bidirectional ports on the Nios to output-pins instead of bidir-pins!

    Cheers,

    Erik
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Just a quick note to say I hit the same problem and used the same solution - changing the clocks and dqs to inout.

    output wire ddr2_ec_local_refresh_ack, // ddr2_ec.local_refresh_ack

    output wire ddr2_ec_local_init_done, // .local_init_done

    output wire ddr2_ec_reset_phy_clk_n, // .reset_phy_clk_n

    output wire [0:0] ddr2_m_mem_odt, // ddr2_m.mem_odt

    inout wire [0:0] ddr2_m_mem_clk, // .mem_clk

    inout wire [0:0] ddr2_m_mem_clk_n, // .mem_clk_n

    output wire [0:0] ddr2_m_mem_cs_n, // .mem_cs_n

    output wire [0:0] ddr2_m_mem_cke, // .mem_cke

    output wire [12:0] ddr2_m_mem_addr, // .mem_addr

    output wire [1:0] ddr2_m_mem_ba, // .mem_ba

    output wire ddr2_m_mem_ras_n, // .mem_ras_n

    output wire ddr2_m_mem_cas_n, // .mem_cas_n

    output wire ddr2_m_mem_we_n, // .mem_we_n

    inout wire [31:0] ddr2_m_mem_dq, // .mem_dq

    inout wire [3:0] ddr2_m_mem_dqs, // .mem_dqs

    output wire [3:0] ddr2_m_mem_dm // .mem_dm