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Altera_Forum
Honored Contributor
11 years agoJust a quick note to say I hit the same problem and used the same solution - changing the clocks and dqs to inout.
output wire ddr2_ec_local_refresh_ack, // ddr2_ec.local_refresh_ack output wire ddr2_ec_local_init_done, // .local_init_done output wire ddr2_ec_reset_phy_clk_n, // .reset_phy_clk_n output wire [0:0] ddr2_m_mem_odt, // ddr2_m.mem_odt inout wire [0:0] ddr2_m_mem_clk, // .mem_clk inout wire [0:0] ddr2_m_mem_clk_n, // .mem_clk_n output wire [0:0] ddr2_m_mem_cs_n, // .mem_cs_n output wire [0:0] ddr2_m_mem_cke, // .mem_cke output wire [12:0] ddr2_m_mem_addr, // .mem_addr output wire [1:0] ddr2_m_mem_ba, // .mem_ba output wire ddr2_m_mem_ras_n, // .mem_ras_n output wire ddr2_m_mem_cas_n, // .mem_cas_n output wire ddr2_m_mem_we_n, // .mem_we_n inout wire [31:0] ddr2_m_mem_dq, // .mem_dq inout wire [3:0] ddr2_m_mem_dqs, // .mem_dqs output wire [3:0] ddr2_m_mem_dm // .mem_dm