FPGA to HPS Peripheral address mapping

Hello,

I am looking into the Cyclone 5 SoC.

The hard processor system (HPS) have a peripheral region from 0xFC000000 - 0xFFFFFFFF.

This region is accessible to the FPGA fabric through the FPGA-to-HPS (F2H) bridge.

On the FPGA side I am forced to use a NiosII processor with MMU for legacy reasons.
Also, I am restricted to Quartus 17.0 (SIL requirement)
Connecting the data master directly to the F2H bridge will not work, because any address in the peripheral region is in the bypass-MMU virtual range.

Adding an Avalon-MM bridge will not work either:

For example, trying to map the bridge at 0x04000000 - 0x04FFFFFF as seen by the NiosII processor.

First, the HPS cannot be mapped to address 0xFC000000, it is not a valid Avalon-MM slave address.

Second, the HPS must be mapped at address 0, because it is address space is 32-bit wide on the 32-bit bus. Trying another offset, QSys say the end address overflows.

Is there any other address-translation bridges that may be used?

Regards,

Ivar Svendsen