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ivar_svendsen's avatar
ivar_svendsen
Icon for New Contributor rankNew Contributor
3 years ago

FPGA to HPS Peripheral address mapping

Hello, I am looking into the Cyclone 5 SoC. The hard processor system (HPS) have a peripheral region from 0xFC000000 - 0xFFFFFFFF. This region is accessible to the FPGA fabric through the FPGA...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for your update. Regarding the address span extender here are some document for your reference:

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/address-span-extender.html

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/using-the-address-span-extender.html


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