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Altera_Forum
Honored Contributor
Honored ContributorEthernet with DSP Dev. Kit Cyclone III (no NIOS)
Hi,
I have the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html). How can I use the Ethernet? In my altera > 80 > ip Directory I have triple_speed_ethernet. Will that work with this board? Or will I need additional IP-Cores? Will they also be shipped with my dev. kit? And are there IP-Cores for USB-Communication? Kind regards, Stefan__66 Replies
Altera_ForumBy NIOS memory I meant any memory that can be accessed by the Nios CPU. So you should be able to read the DDR SDRAM too.
For the SDRAM access, it really depends on how you do it. If you put the DDR controller in the SOPC system, your custom IP and the NIOS can share access to the RAM. Arbitration will be made automatically by SOPC builder. Your custom IP will need to use an Avalon master interface to wlite to the RAM. Another alternative could be to use a ready made DMA IP to write the data to RAM for you. If you format your data in Avalon streams, you can use the SGDMA IP to transfer it to RAM.- Altera_Forum
As you said it in your previous post, it is possible in principle to have the FPGA and the NIOS CPU running at the same time (and sharing access to SDRAM, for example). So this would be one easy solution. Yesterday I tried to do the simple socket server example [...] (http://www.alteraforum.com/forum/showthread.php?p=73770), which is also working now finally.
After all, I decided to give coding the ethernet/ip/udp protocol in hardware a try. I already know what documents I have to read in general for this purpose: UDP: rfc 768 - user datagram protocol (http://tools.ietf.org/html/rfc768) (It's much simpler than tcp (http://tools.ietf.org/html/rfc793)) IP: rfc 791 - internet protocol (http://tools.ietf.org/html/rfc791) Ethernet: rfc 826 - ethernet address resolution protocol (http://tools.ietf.org/html/rfc826) <--- is this the right document?? Maybe it's not that difficult as I thought. I should give it a try at least. If it doesn't work I will have to use the NIOS as an ethernet driver, because it doesn't seem that I will get very far with USB. - Altera_Forum
The RFC 826 is just the ARP protocol, i.e. the protocol that can give you a MAC address from an IP address. It is not the easiest to read, I'm sure other online resources that can give a more readable information.
You should have a more detailed look at the UDP offload example, it is well documented. IIRC they still use the NIOS to get the mac address through the ARP protocol, and then feed the hardware with the correct information to generate the UDP/IP/Ethernet packets. - Altera_Forum--- Quote Start --- The RFC 826 is just the ARP protocol, i.e. the protocol that can give you a MAC address from an IP address. It is not the easiest to read, I'm sure other online resources that can give a more readable information. --- Quote End --- There are many (http://www.faqs.org/rfcs/np.html#eth) of ethernet related rfc. Maybe it's better explained in wikipedia: http://en.wikipedia.org/wiki/ethernet#physical_layer What do you think is better? --- Quote Start --- You should have a more detailed look at the UDP offload example, it is well documented. --- Quote End --- Yes, I will do that later. If I try to use triple speed ethernet (without NIOS) then I think I don't need the SOPC Builder, or do I need it? I added triple speed ethernet megafunction. But at the moment I am not sure how to connect all the pins. In my hardware reference manual I have 16 address lines, but the TSE IP-Core has only 8 address lines... I guess the data lines are bidirectional, so I have chosen the pins 'bidir' and assigned them according to the data sheet. But if I connect the ff_tx_data and ff_rx_data (of the triple speed ethernet core) to the 32 Bit Data-Line, there come errors:
Found I/O cells that do not connect to top-level pins or have illegal connectivity - Altera_Forum
The Wikipedia page is easier to read, and accurate AFAIK.
If you don't use the Nios, you don't need to go through SOPC builder and can directly use the Megawizard to create your instance. I don't know what reference manual you are talking about, but the datasheet (http://www.altera.com/literature/ug/ug_ethernet.pdf) mentions 8 address lines. All the signals are unidirectionnal, you have separate read and write data vectors. The TSE core uses Avalon memory mapped and streams interfaces, and you can learn more about them here (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf?gsa_pos=7&wt.oss_r=1&wt.oss=avalon). - Altera_Forum--- Quote Start --- All the signals are unidirectionnal, you have separate read and write data vectors. The TSE core uses Avalon memory mapped and streams interfaces, and you can learn more about them here. --- Quote End --- On the TSE core I have following data lines: inputs: writedata[31..0] (Avalon-MM Register Interface Signal) ff_tx_data[31..0] (Avalon-ST Transmit Interface Signal) outputs: ff_rx_data[31..0] (Avalon-ST Receive Interface Signal) readdata[31..0] (Avalon-MM Register Interface Signal) I think, the above mentioned data lines must not be connected to the external PHY Pins of the FPGA. Is that right? Instead, I should connect gm_rx/tx or rgmii_in/out or m_rx/tx to the PHY Pins. But in the dev kit datasheet (http://www.altera.com/literature/manual/mnl_nios2_board_cycloneii_2c35.pdf) (I am working with cyclone II Board, my cyclone III DSP is not yet delivered) the Data Lines have only numbers, not symbol names. So I don't know which of them to use: Pin D8 = Data Line fe_d0 Pin C8 = Data Line fe_d1 Pin F10 = Data Line fe_d2 ... Pin G11 = Data Line fe_d31
- Altera_Forum
You can't use the TSE with the Cyclone II board. On that dev kit the MAC is on the board.
- Altera_Forum
And to answer your last question, yes the gm_* / rgmii_* / m_* are the signals to connect to the PHY, depending on the interface with the PHY. On the Cyclone III board it is an RGMII interface.
- Altera_Forum
OK. I think I am making good progress. :)
Now I created a VHDL core (FPGA) which is connected to the MAC. I am wondering how I can send my packet from the FPGA to the MAC. I would do it like this: (this is no valid VHDL syntax, it is only for showing the concept)
Is this a correct beginning?address = 0x0 data = ... (first 4 byte of the packet) --> falling/rising edge of signal_write address = 0x1 data = ... (second 4 byte of the packet) --> falling/rising edge of signal_write ... --> transmit the created packet (how?) - Altera_Forum
No it doesn't work that way. The Avalon memory mapped interface is only used to configure the registers in the mac.
You will need to set up a few registers to enable and configure the Mac. For that you supply the address and data on address and write_data, put a '1' on the write signal, and wait for waitrequest to go back to '0'. Then you can write another value. To send a packet, you need to use the Avalon stream sink ff_tx. You don't have any address there, just send your words one after the others and use the rdy/wren for flow control. Those interfaces are described in the Avalon spec.
