Honored ContributorHi,
I have the dsp development kit, cyclone iii edition (http://www.altera.com/products/devkits/altera/kit-cyc3-dsp.html). How can I use the Ethernet? In my altera > 80 > ip Directory I have triple_speed_ethernet. Will that work with this board? Or will I need additional IP-Cores? Will they also be shipped with my dev. kit? And are there IP-Cores for USB-Communication? Kind regards, Stefan__
Honored ContributorBy NIOS memory I meant any memory that can be accessed by the Nios CPU. So you should be able to read the DDR SDRAM too.
For the SDRAM access, it really depends on how you do it. If you put the DDR controller in the SOPC system, your custom IP and the NIOS can share access to the RAM. Arbitration will be made automatically by SOPC builder. Your custom IP will need to use an Avalon master interface to wlite to the RAM. Another alternative could be to use a ready made DMA IP to write the data to RAM for you. If you format your data in Avalon streams, you can use the SGDMA IP to transfer it to RAM.Honored ContributorAs you said it in your previous post, it is possible in principle to have the FPGA and the NIOS CPU running at the same time (and sharing access to SDRAM, for example). So this would be one easy solution. Yesterday I tried to do the simple socket server example [...] (http://www.alteraforum.com/forum/showthread.php?p=73770), which is also working now finally.
After all, I decided to give coding the ethernet/ip/udp protocol in hardware a try. I already know what documents I have to read in general for this purpose: UDP: rfc 768 - user datagram protocol (http://tools.ietf.org/html/rfc768) (It's much simpler than tcp (http://tools.ietf.org/html/rfc793)) IP: rfc 791 - internet protocol (http://tools.ietf.org/html/rfc791) Ethernet: rfc 826 - ethernet address resolution protocol (http://tools.ietf.org/html/rfc826) <--- is this the right document?? Maybe it's not that difficult as I thought. I should give it a try at least. If it doesn't work I will have to use the NIOS as an ethernet driver, because it doesn't seem that I will get very far with USB.Honored ContributorThe RFC 826 is just the ARP protocol, i.e. the protocol that can give you a MAC address from an IP address. It is not the easiest to read, I'm sure other online resources that can give a more readable information.
You should have a more detailed look at the UDP offload example, it is well documented. IIRC they still use the NIOS to get the mac address through the ARP protocol, and then feed the hardware with the correct information to generate the UDP/IP/Ethernet packets.Honored Contributor
Found I/O cells that do not connect to top-level pins or have illegal connectivity
The Wikipedia page is easier to read, and accurate AFAIK.
If you don't use the Nios, you don't need to go through SOPC builder and can directly use the Megawizard to create your instance. I don't know what reference manual you are talking about, but the datasheet (http://www.altera.com/literature/ug/ug_ethernet.pdf) mentions 8 address lines. All the signals are unidirectionnal, you have separate read and write data vectors. The TSE core uses Avalon memory mapped and streams interfaces, and you can learn more about them here (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf?gsa_pos=7&wt.oss_r=1&wt.oss=avalon).Honored ContributorHonored ContributorYou can't use the TSE with the Cyclone II board. On that dev kit the MAC is on the board.
Honored ContributorAnd to answer your last question, yes the gm_* / rgmii_* / m_* are the signals to connect to the PHY, depending on the interface with the PHY. On the Cyclone III board it is an RGMII interface.
Honored ContributorOK. I think I am making good progress. :)
Now I created a VHDL core (FPGA) which is connected to the MAC. I am wondering how I can send my packet from the FPGA to the MAC. I would do it like this: (this is no valid VHDL syntax, it is only for showing the concept)address = 0x0
data = ... (first 4 byte of the packet)
--> falling/rising edge of signal_write
address = 0x1
data = ... (second 4 byte of the packet)
--> falling/rising edge of signal_write
...
--> transmit the created packet (how?)No it doesn't work that way. The Avalon memory mapped interface is only used to configure the registers in the mac.
You will need to set up a few registers to enable and configure the Mac. For that you supply the address and data on address and write_data, put a '1' on the write signal, and wait for waitrequest to go back to '0'. Then you can write another value. To send a packet, you need to use the Avalon stream sink ff_tx. You don't have any address there, just send your words one after the others and use the rdy/wren for flow control. Those interfaces are described in the Avalon spec.
