Ethernet with DSP Dev. Kit Cyclone III (no NIOS)

OK. I think I am making good progress. :)

Now I created a VHDL core (FPGA) which is connected to the MAC. I am wondering how I can send my packet from the FPGA to the MAC. I would do it like this:

(this is no valid VHDL syntax, it is only for showing the concept)

address = 0x0
data = ... (first 4 byte of the packet)
--> falling/rising edge of signal_write
address = 0x1
data = ... (second 4 byte of the packet)
--> falling/rising edge of signal_write
...
--> transmit the created packet (how?)

Is this a correct beginning?