Ethernet with DSP Dev. Kit Cyclone III (no NIOS)

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All the signals are unidirectionnal, you have separate read and write data vectors. The TSE core uses Avalon memory mapped and streams interfaces, and you can learn more about them here.

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On the TSE core I have following data lines:

inputs:

writedata[31..0] (Avalon-MM Register Interface Signal)

ff_tx_data[31..0] (Avalon-ST Transmit Interface Signal)

outputs:

ff_rx_data[31..0] (Avalon-ST Receive Interface Signal)

readdata[31..0] (Avalon-MM Register Interface Signal)

I think, the above mentioned data lines must not be connected to the external PHY Pins of the FPGA. Is that right?

Instead, I should connect gm_rx/tx or rgmii_in/out or m_rx/tx to the PHY Pins. But in the dev kit datasheet (http://www.altera.com/literature/manual/mnl_nios2_board_cycloneii_2c35.pdf) (I am working with cyclone II Board, my cyclone III DSP is not yet delivered) the Data Lines have only numbers, not symbol names. So I don't know which of them to use:

Pin D8 = Data Line fe_d0

Pin C8 = Data Line fe_d1

Pin F10 = Data Line fe_d2

...

Pin G11 = Data Line fe_d31