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Hello leo12345678,

Thank you for posting on the Intel® communities.

We would like to inform you that we have a forum for these specific issues and products, so we are moving it to the "FPGA, SoC, And CPLD Boards And Kits" forum so you can get better support for this matter.

• https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/bd-p/fpga-soc-cpld-boards-kits

Regards,

Deivid A.

Intel Customer Support Technician

Hi Leo12345678,

1， 阻抗异常低具体指什么？是指 FPGA 某些引脚到GND的电阻过低吗？

2， 是在芯片还未使用之前进行测试的，还是把 FPGA 焊在板子上之后再进行测试的？

3， 请问具体是怎么测试的？对于FPGA的 I/O 引脚，一般推荐的测试方法是进行 I/V 曲线测试。具体来说就是：1）将稳压电源，电源正极连接待测 I/O引脚，负极连接GND；2）控制电流在100mA以下，电压在引脚能够承受的最大电压值以下；3）测量-0.5V~最大电压之间不同电压下的电流，以获得一个I/V曲线。一般不推荐使用万用表测量，因为引脚不是纯阻性结构，且万用表内部的电源电压可能超过引脚能承受的最大电压。

1. What does "abnormally low impedance" refer to? Does it mean that the resistance from certain FPGA pins to GND is too low?

2. Was the testing conducted before the chip was used, or after the FPGA soldered onto the board ?

3. How was the specific testing conducted? The recommended testing method for FPGA I/O pins is to perform I/V curve testing. Specifically, it means: 1) Connecting the positive pole of the regulated power supply to the I/O pin to be tested, and the negative pole to GND; 2) Control the current below 100mA and the voltage below the maximum voltage that the pin can withstand; 3) Measure the current at different voltages between -0.5V and the maximum voltage to obtain an I/V curve. It is generally not recommended to use a multimeter for measurement because the pins are not of pure resistive structure, and the internal power voltage of the multimeter may exceed the maximum voltage that the pins can withstand.

Thanks & Regards,

Xiaoyan

您好
1.是指 FPGA 某些引脚到GND的电阻过高
2.具体操作图片见附件，是贴到板子上做的测试
我们想确认一下这款FPGA芯片你们是否有管理单体阻抗，是否有内控标准，帮忙确认一下，谢谢

Hi leo12345678,

​

对于​FPGA的引脚阻抗，我们没有提供明确的标准。

​

从您提供的测试流程来看，主要​想要测试的是 1.2 V 供电引脚 (H11 VCCINT) 是否有对地的阻抗问题对吗？

从测试结果来看，最终结果是​“NG 板子的 FPGA 芯片 1.2v 对地阻抗为 18.55Ω；OK 板子上的 FPGA 芯片的 1.2v 对地阻抗为 34Ω”。是单一的电阻结果。

​

正如我前面提到的​，我们推荐的测试方法是进行I/V曲线测试。因为FPGA引脚不是纯阻性结构，如果只有单一的电阻值，实际上无法判断引脚是否产生了损坏。获取I/V曲线之后，观察 0V 电压附近是否出现了阻性的电流表现（正常的I/O在 0V 电阻附近应该不出现导通电流）。

We did not provide a clear standard for the pin impedance of FPGA.

From the testing process you provided, the main thing you want to test is whether there is an impedance problem to ground from the 1.2 V power supply pin (H11 VCCINT), right?

From the test results, the final result is that "the 1.2v impedance of the FPGA chip on the NG board to ground is 18.55 Ω; the 1.2v impedance of the FPGA chip on the OK board to ground is 34 Ω." It is a single resistance result.

As I mentioned in the previous message, our recommended testing method is to perform I/V curve test. Because FPGA pins are not pure resistive structures, if only a single resistance value is used, we are not able to determine whether the pins have been damaged. After obtaining the I/V curve, observe whether there is resistive current near the 0V voltage (normal I/O should not have conduction current near the 0V resistance).

​

Thanks & Regards,

Xiaoyan

Hi there,

还有更多问题吗？

Any further questions?

Thanks & Regards,

Xiaoyan