EP4CE75U19I7N

Hi Leo12345678,

1， 阻抗异常低具体指什么？是指 FPGA 某些引脚到GND的电阻过低吗？

2， 是在芯片还未使用之前进行测试的，还是把 FPGA 焊在板子上之后再进行测试的？

3， 请问具体是怎么测试的？对于FPGA的 I/O 引脚，一般推荐的测试方法是进行 I/V 曲线测试。具体来说就是：1）将稳压电源，电源正极连接待测 I/O引脚，负极连接GND；2）控制电流在100mA以下，电压在引脚能够承受的最大电压值以下；3）测量-0.5V~最大电压之间不同电压下的电流，以获得一个I/V曲线。一般不推荐使用万用表测量，因为引脚不是纯阻性结构，且万用表内部的电源电压可能超过引脚能承受的最大电压。

1. What does "abnormally low impedance" refer to? Does it mean that the resistance from certain FPGA pins to GND is too low?

2. Was the testing conducted before the chip was used, or after the FPGA soldered onto the board ?

3. How was the specific testing conducted? The recommended testing method for FPGA I/O pins is to perform I/V curve testing. Specifically, it means: 1) Connecting the positive pole of the regulated power supply to the I/O pin to be tested, and the negative pole to GND; 2) Control the current below 100mA and the voltage below the maximum voltage that the pin can withstand; 3) Measure the current at different voltages between -0.5V and the maximum voltage to obtain an I/V curve. It is generally not recommended to use a multimeter for measurement because the pins are not of pure resistive structure, and the internal power voltage of the multimeter may exceed the maximum voltage that the pins can withstand.

Thanks & Regards,

Xiaoyan