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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
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EMIF Location constraint error

Hi

I am getting below error while building a Quartus project using Agilex board (DK-DEV-AGI027-RA) with DDR4 component 1 memory.

I used following pin constraints,

"set_location_assignment PIN_AV33 -to emif_fm_0_mem_mem_ck[1][0]" which is correct as per schematic shared in the https://cdrdv2.intel.com/v1/dl/getContent/819447.

Error summary.

"Error (175020): The Fitter cannot place logic EMIF_GROUP that is part of External Memory Interfaces (EMIF) IP emif_altera_emif_fm_276_fwujoli in region (226, 333) to (322, 333), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The EMIF_GROUP name(s): EMIF_0_emif_altera_emif_fm_276_fwujoli
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: NON_HPS_EMIF (1 location affected)
Info (175029): EMIF_GROUP containing J9
Info (175015): The I/O pad emif_fm_0_mem_mem_ck[1][0] is constrained to the location PIN_AV33 due to: User Location Constraints (PIN_AV33)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within a ADDR_CMD_GRP, which is contained within this EMIF_GROUP"

Can you please check what could be the possible cause of this error.

Thanks & regards

Madhur

Board Debug
Fpga Devkit
  • mjuneja2007's avatar
    mjuneja2007
    5 months ago

    Hello Adzim

    I was able to resolve the above issue, by selecting the checkbox "Mimic HPS EMIF" in External Memory Interfaces (EMIF) IP wizard, if we want to connect EMIF in FPGA fabric to DDR4 component 1.

    So now we can close this issue

    regards

    Madhur

8 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi Madhur,


    I think the Fitter error is better to debug through the design.

    Can you share the design to replicate the issue?


    Regards,

    Adzim



  • mjuneja2007's avatar
    mjuneja2007
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hello Adzim

    Actually I am connecting the said pin constraint(AV_33) of DDR4 component 1 to FPGA fabric but I think DDR4 component 1 is connected to HPS not the FPGA fabric.

    Can you please confirm the same.

    Thanks & regards

    Madhur

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi Madhur,


    The connection here is connected to FPGA. Just the IP can do connection HPS.

    If you use the HPS EMIF IP, then the FPGA should has connection to HPS.

    If you use the FPGA EMIF IP, then the FPGA should not has connection to HPS.

    The pin location is same for both IP in this case.


    I think you need to set all pin location for EMIF interface similar to the schematic.

    But the pin name is emif_fm_0_mem_mem_ck[1][0]. It is second CK pin in the IP?

    The schematic only has 1 pair of CK pin. Is there any other CK pin in the design?


    Regards,

    Adzim


  • mjuneja2007's avatar
    mjuneja2007
    Icon for Occasional Contributor rankOccasional Contributor
    6 months ago

    Hello Adzim

    The pin name is emif_fm_0_mem_mem_ck[1][0], because I was trying to instantiate two EMIF IPs connecting to DDR components comp 0 and comp 1 on Agilex board.

    But even I try to connect one EMIF IP to comp 1 pin mapping, error still comes, while it doesn't come for comp 0 interface.

    Even the error says "there are no valid locations in the region for logic of this type".

    And then I found this below link, https://www.intel.com/content/www/us/en/content-details/656512/intel-agilex-7-i-series-agib027-device-pinouts-xlsx-format-alt-format-pdf.html

    according which Comp 1 pin maps are tied to HPS_DDR. Can you please confirm the same.

    regards

    Madhur

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi Madhur,


    Can you provide the design in this thread?


    If you have two EMIF IP, the IP name should be emif_fm_0 and emif_fm_1.

    The HPS_DDR is the HPS function. If you don't use the HPS EMIF IP, then IO will be functioning as FPGA.

    Placing the pin in this location should be okay.


    I suspect there are something wrong with the top level design.

    If cannot share the design, please share the all EMIF signals names for both EMIF IPs.



    Regards,

    Adzim


  • mjuneja2007's avatar
    mjuneja2007
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hello Adzim

    I was able to resolve the above issue, by selecting the checkbox "Mimic HPS EMIF" in External Memory Interfaces (EMIF) IP wizard, if we want to connect EMIF in FPGA fabric to DDR4 component 1.

    So now we can close this issue

    regards

    Madhur