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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
Solved

EMIF Location constraint error

Hi I am getting below error while building a Quartus project using Agilex board (DK-DEV-AGI027-RA) with DDR4 component 1 memory. I used following pin constraints, "set_location_assignment PIN_AV3...
Board Debug
Fpga Devkit
  • mjuneja2007's avatar
    mjuneja2007
    5 months ago

    Hello Adzim

    I was able to resolve the above issue, by selecting the checkbox "Mimic HPS EMIF" in External Memory Interfaces (EMIF) IP wizard, if we want to connect EMIF in FPGA fabric to DDR4 component 1.

    So now we can close this issue

    regards

    Madhur

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi Madhur,


The connection here is connected to FPGA. Just the IP can do connection HPS.

If you use the HPS EMIF IP, then the FPGA should has connection to HPS.

If you use the FPGA EMIF IP, then the FPGA should not has connection to HPS.

The pin location is same for both IP in this case.


I think you need to set all pin location for EMIF interface similar to the schematic.

But the pin name is emif_fm_0_mem_mem_ck[1][0]. It is second CK pin in the IP?

The schematic only has 1 pair of CK pin. Is there any other CK pin in the design?


Regards,

Adzim