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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

EMIF Location constraint error

Hi I am getting below error while building a Quartus project using Agilex board (DK-DEV-AGI027-RA) with DDR4 component 1 memory. I used following pin constraints, "set_location_assignment PIN_AV3...
Board Debug
Fpga Devkit
  • mjuneja2007's avatar
    mjuneja2007
    1 year ago

    Hello Adzim

    I was able to resolve the above issue, by selecting the checkbox "Mimic HPS EMIF" in External Memory Interfaces (EMIF) IP wizard, if we want to connect EMIF in FPGA fabric to DDR4 component 1.

    So now we can close this issue

    regards

    Madhur

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Madhur,


Can you provide the design in this thread?


If you have two EMIF IP, the IP name should be emif_fm_0 and emif_fm_1.

The HPS_DDR is the HPS function. If you don't use the HPS EMIF IP, then IO will be functioning as FPGA.

Placing the pin in this location should be okay.


I suspect there are something wrong with the top level design.

If cannot share the design, please share the all EMIF signals names for both EMIF IPs.



Regards,

Adzim