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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

EMIF Location constraint error

Hi I am getting below error while building a Quartus project using Agilex board (DK-DEV-AGI027-RA) with DDR4 component 1 memory. I used following pin constraints, "set_location_assignment PIN_AV3...
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Fpga Devkit
  • mjuneja2007's avatar
    mjuneja2007
    1 year ago

    Hello Adzim

    I was able to resolve the above issue, by selecting the checkbox "Mimic HPS EMIF" in External Memory Interfaces (EMIF) IP wizard, if we want to connect EMIF in FPGA fabric to DDR4 component 1.

    So now we can close this issue

    regards

    Madhur

mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hello Adzim

The pin name is emif_fm_0_mem_mem_ck[1][0], because I was trying to instantiate two EMIF IPs connecting to DDR components comp 0 and comp 1 on Agilex board.

But even I try to connect one EMIF IP to comp 1 pin mapping, error still comes, while it doesn't come for comp 0 interface.

Even the error says "there are no valid locations in the region for logic of this type".

And then I found this below link, https://www.intel.com/content/www/us/en/content-details/656512/intel-agilex-7-i-series-agib027-device-pinouts-xlsx-format-alt-format-pdf.html

according which Comp 1 pin maps are tied to HPS_DDR. Can you please confirm the same.

regards

Madhur