DE3 DDR2 demo does not work with Quartus v9.1

Terasic helped provide a solution. there seem to be enough differences between v8 and v9 of quartus to warrent these changes. this also allows 1G access using NIOS using these settings:

in SOPC Builder add the DDR2 SDRAM High Performance Controller and customize it with these settings for the DE3:

Speed grade: 2

PLL ref clock: 50

memory clock freq: 266.667

controller data rate: half

and then click modify parameters and set these:

<?xml version="1.0" encoding="UTF-8"?>

<preset name="Custom (DE3 1G 667 SODIMM)">

<parameter name="mem_if_memtype" value="DDR2 SDRAM" />

<parameter name="vendor" value="JEDEC" />

<parameter name="chip_or_dimm" value="Unbuffered DIMM" />

<parameter name="mem_fmax" value="333.3" />

<parameter name="mem_if_coladdr_width" value="10" />

<parameter name="mem_if_rowaddr_width" value="14" />

<parameter name="mem_if_bankaddr_width" value="2" />

<parameter name="mem_if_clk_pair_count" value="2" />

<parameter name="mem_if_cs_per_dimm" value="2" />

<parameter name="mem_if_cs_width" value="2" />

<parameter name="mem_if_dq_per_dqs" value="8" />

<parameter name="mem_if_dwidth" value="64" />

<parameter name="mem_if_pchaddr_bit" value="10" />

<parameter name="mem_if_dm_pins_en" value="Yes" />

<parameter name="mem_if_tinit_us" value="200.0" />

<parameter name="mem_if_tmrd_ns" value="8.0" />

<parameter name="mem_if_tras_ns" value="45.0" />

<parameter name="mem_if_trcd_ns" value="15.0" />

<parameter name="mem_if_trp_ns" value="15.0" />

<parameter name="mem_if_trefi_us" value="7.8" />

<parameter name="mem_if_trfc_ns" value="105.0" />

<parameter name="mem_if_twr_ns" value="15.0" />

<parameter name="mem_if_twtr_ck" value="2" />

<parameter name="mem_tac_ps" value="500" />

<parameter name="mem_tdqsck_ps" value="450" />

<parameter name="mem_tdqsq_ps" value="240" />

<parameter name="mem_tdqss_ck" value="0.25" />

<parameter name="mem_tdha_ps" value="175" />

<parameter name="mem_tdsa_ps" value="100" />

<parameter name="mem_tdsh_ck" value="0.2" />

<parameter name="mem_tdss_ck" value="0.2" />

<parameter name="mem_tiha_ps" value="275" />

<parameter name="mem_tisa_ps" value="200" />

<parameter name="mem_tqhs_ps" value="400" />

<parameter name="mem_tfaw_ns" value="0.0" />

<parameter name="mem_trrd_ns" value="7.5" />

<parameter name="mem_trtp_ns" value="7.5" />

<parameter name="mem_bl" value="4" />

<parameter name="mem_btype" value="Sequential" />

<parameter name="mem_dll_en" value="Yes" />

<parameter name="mem_drv_str" value="Normal" />

<parameter name="mem_odt" value="50" />

<parameter name="mem_tcl" value="5.0" />

<parameter name="mem_atcl" value="Disabled" />

<parameter name="mem_tcl_30_fmax" value="200.0" />

<parameter name="mem_tcl_40_fmax" value="266.667" />

<parameter name="mem_tcl_50_fmax" value="333.3" />

<parameter name="mem_tcl_60_fmax" value="333.3" />

</preset>

in the top level design, use these connections:

.global_reset_n_to_the_altmemddr(system_reset_n),

.local_init_done_from_the_altmemddr(),

.local_refresh_ack_from_the_altmemddr(),

.local_wdata_req_from_the_altmemddr(),

.mem_addr_from_the_altmemddr(mem_addr),

.mem_ba_from_the_altmemddr(mem_ba),

.mem_cas_n_from_the_altmemddr(mem_cas_n),

.mem_cke_from_the_altmemddr(mem_cke),

.mem_clk_n_to_and_from_the_altmemddr(mem_clk_n),

.mem_clk_to_and_from_the_altmemddr(mem_clk),

.mem_cs_n_from_the_altmemddr(mem_cs_n),

.mem_dm_from_the_altmemddr(mem_dm),

.mem_dq_to_and_from_the_altmemddr(mem_dq),

.mem_dqs_to_and_from_the_altmemddr(mem_dqs),

.mem_dqsn_to_and_from_the_altmemddr(mem_dqsn),

.mem_odt_from_the_altmemddr(mem_odt),

.mem_ras_n_from_the_altmemddr(mem_ras_n),

.mem_we_n_from_the_altmemddr(mem_we_n),

.oct_ctl_rs_value_to_the_altmemddr(),

.oct_ctl_rt_value_to_the_altmemddr(),

.reset_phy_clk_n_from_the_altmemddr(),

and to meet timing, make sure to modify these under assignments:settings

- Analysis & Synthesis: more settings: Parallel Synthesis ON

- Analysis & Synthesis: Timing-Driven Synthesis checked

- Analysis & Synthesis: Balanced

- add derive_pll_clocks to top level .sdc

- make sure top level .sdc and altmemddr_...sdc are in timequest timing analyzer

- Fitter Settings: more: enable Beneficial Skew Optimization ON

- Fitter Settings: optimize hold timing = All Paths

I tried what you said but the demo still fail.is there any other suggestion?

and where did you find this solution?

attached is a settings file, the top level .v file, the voltage setting .v file, and the .sopc file

start a new project and incorporate these into the design.

Ok, i tried the DDR2 test with the files i got from elmoos, but i still don't get it working.

I created a new Projekt with bsp and copied the test source files into it.

when i run the test (press button 01) the test starts, but then te cpu is kind of reseted.

In the console i get things like this:

===== DE3 DDR2 Test Program =====
DDR2 Clock: 266.6 MHZ
DDR2  Size: 1024 MBytes
==========================================================
Press any BUTTON to start test  
write...
===== DE3 DDR2 Test Program =====
===== DE3 DDR2 Test Program =====
DDR2 Clock: 266.6 MHZ
DDR2  Size: 1024 MBytes
=============== DE3 DDR2 Test Program =====
===== DE3 DDR2 Test Program =====
DDR2 Clock: 266.6 MHZ
DDR2  Size: 1024 MBytes
=============== DE3 DDR2 Test Program =====
===== DE3 DDR2 Test Program =====
DDR2 Clock: 266.6 MHZ
DDR2  Size: 1024 MBytes
==========================================================
Press any BUTTON to start test  
write...
===== DE3 DDR2 Test Program =====

Show Progress is defined. undfining doesent help eighter.

Also there seems to be a problem with printf. somtimes it doesn't print.

Any ideas??

(the i2c test works when defined, does this mean the ddr works??)

Hello,

i used the ddr2-rank2 roject, as well as the software that was in the ./software folder of the projekt.

I had to comment three lines out which would print the rank and two other things, cause these werent found somehow.

Which software did you use? the one in the projekt or the original one?

when i use the memorytest from template (new projekt and bsp->memory test) the system seems to reset too.

<---->   Nios II Memory Test.   <---->
This software example tests the memory in your system to assure it
is working properly.  This test is destructive to the contents of
the memory it tests. Assure the memory being tested does not contain
the executable or data sections of this code or the exception address
of the system.
----------------------------------
      Memory Test Main Menu
----------------------------------
     a:  Test RAM
     b:  Test Flash
     q:  Exit
----------------------------------
Select Choice (a-b): 
a
Base address to start memory test: (i.e. 0x800000)
>
0x00000000
End Address:
>
0x03fffffff
Testing RAM from 0x0 to 0x3FFFFFFF
             <---->   Nios II Memory Test.   <---->
This software example tests the memory in your system to assure it
is working properly.  This test is destructive to the contents of
the memory it tests. Assure the memory being tested does not contain
the executable or data sections of this code or the exception address
of the system.
----------------------------------
      Memory Test Main Menu
----------------------------------
     a:  Test RAM
     b:  Test Flash
     q:  Exit
----------------------------------

this looks like some error in the quartus model then? everytime i try to access memory i get a reset.

EDIT:

i tested somethoing differnt now.

my memory is from 0x00000000 to 0x3fffffff

when i test it from eg 0x00000000 to 0x00010000 or from 0x10000000 to 0x20000000 it works fine.

that means the mempory doesnt work correctly? but why does the testprogram crash and i'm not getting an error?