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ETang2's avatar
ETang2
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

DE10-Lite and sdram controller ip

Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supp...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi ETang2 
 

Please let me know if you have any further question.
 

Regards,

Adzim

Thierry29's avatar
Thierry29
Icon for New Contributor rankNew Contributor
1 day ago

Hi,

I followed the same procedure to use the "altera_avalon_new_sdram_controller" in a Quartus Lite v25.1 project including a Nios V/m processor for the DE10-Lite board.

The Quartus project including the SDRAM controller compiles correctly. Next the BSP is created followed by the top makefile. The application program is a simple "hello world" (full project attached as an archive - de10_lite_25_1_sdram.zip)

I am encountering a compilation issue when the SDRAM is used. Specifically the problem occurs during the object code linking stage.

1) When only onchip memory is selected in the BSP editor (linker script tab), everything works correctly. Compilation generates an .elf file, and the code executes successfully.

2) When a code section is placed in the SDRAM, the compilation fails. See, for example, the screenshots of BSP editor and Ashling RiscFree IDE: BSP_Onchip_and_SDRAM.png and Errors_Onchip_and_SDRAM.png.

3) When all sections are placed in the SDRAM (except .entry), compilation fails with a slightly different error message. See, for example, the screenshots of BSP editor and Ashling RiscFree IDE: BSP_SDRAM_only.png and Errors_SDRAM_only.png.

The main error message is "helloworld.elf section `.entry' will not fit in region `reset'". Does anyone have an idea what might be wrong in the project and how to resolve this issue?

Thanks a lot for your help.

Thierry