Data from FPGA to host

Can you please delete the ./libraries folder that the error message is referring to, and try again.

Which version of Quartus II are you using to generate your Qsys system? The version of Quartus and Modelsim need to be consistent.

Cheers,

Dave

I've started a new tutorial from scratch. I use Quartus II 13.1 and Modelsim ALTERA 10.1d. the "elab +nowarnTFMPC" gives:

elab +nowarnTFMPC#   elab #  vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system #  ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.#  Error loading design

I'll see with my administrator for the license...

With the ASE version I get:

 vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L altera_common_sv_packages# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012#  -- Compiling module qsys_system_bfm_master_tb#  -- Importing package altera_common_sv_packages.verbosity_pkg#  -- Importing package altera_common_sv_packages.avalon_mm_pkg#  #  Top level modules:#      qsys_system_bfm_master_tb
set TOP_LEVEL_NAME qsys_system_bfm_master_tb#  qsys_system_bfm_master_tb
elab +nowarnTFMPC#   elab #  vsim +nowarnTFMPC -L work -L work_lib -L altera_common_sv_packages -L rsp_xbar_mux -L rsp_xbar_demux -L cmd_xbar_mux -L cmd_xbar_demux -L limiter -L id_router -L addr_router -L led_pio_s1_translator_avalon_universal_slave_0_agent -L bfm_master_m0_translator_avalon_universal_master_0_agent -L led_pio_s1_translator -L bfm_master_m0_translator -L p2b_adapter -L b2p_adapter -L transacto -L p2b -L b2p -L fifo -L timing_adt -L jtag_phy_embedded_in_jtag_master -L rst_controller -L mm_interconnect_0 -L onchip_ram -L button_pio -L led_pio -L jtag_master -L bfm_master -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -t ps qsys_system_bfm_master_tb #  Loading sv_std.std#  Loading altera_common_sv_packages.verbosity_pkg#  Loading altera_common_sv_packages.avalon_mm_pkg#  Loading work.qsys_system_bfm_master_tb#  Loading work.qsys_system#  Loading altera_common_sv_packages.avalon_utilities_pkg#  Loading bfm_master.altera_avalon_mm_master_bfm#  Loading jtag_master.qsys_system_jtag_master#  Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_jtag_interface#  Loading timing_adt.qsys_system_jtag_master_timing_adt#  Loading limiter.altera_avalon_sc_fifo#  Loading b2p.altera_avalon_st_bytes_to_packets#  Loading p2b.altera_avalon_st_packets_to_bytes#  Loading transacto.altera_avalon_packets_to_master#  Loading b2p_adapter.qsys_system_jtag_master_b2p_adapter#  Loading p2b_adapter.qsys_system_jtag_master_p2b_adapter#  Loading rst_controller.altera_reset_controller#  Loading led_pio.qsys_system_led_pio#  Loading button_pio.qsys_system_button_pio#  Loading onchip_ram.qsys_system_onchip_ram#  Loading altera_mf_ver.altsyncram#  Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES#  Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION#  Loading mm_interconnect_0.qsys_system_mm_interconnect_0#  Loading bfm_master_m0_translator.altera_merlin_master_translator#  Loading led_pio_s1_translator.altera_merlin_slave_translator#  Loading bfm_master_m0_translator_avalon_universal_master_0_agent.altera_merlin_master_agent#  Loading led_pio_s1_translator_avalon_universal_slave_0_agent.altera_merlin_slave_agent#  Loading led_pio_s1_translator_avalon_universal_slave_0_agent.altera_merlin_burst_uncompressor#  Loading addr_router.qsys_system_mm_interconnect_0_addr_router#  Loading addr_router.qsys_system_mm_interconnect_0_addr_router_default_decode#  Loading id_router.qsys_system_mm_interconnect_0_id_router#  Loading id_router.qsys_system_mm_interconnect_0_id_router_default_decode#  Loading limiter.altera_merlin_traffic_limiter#  Loading cmd_xbar_demux.qsys_system_mm_interconnect_0_cmd_xbar_demux#  Loading cmd_xbar_mux.qsys_system_mm_interconnect_0_cmd_xbar_mux#  Loading cmd_xbar_mux.altera_merlin_arbitrator#  Loading cmd_xbar_mux.altera_merlin_arb_adder#  Loading rsp_xbar_demux.qsys_system_mm_interconnect_0_rsp_xbar_demux#  Loading rsp_xbar_mux.qsys_system_mm_interconnect_0_rsp_xbar_mux#  Loading rsp_xbar_mux.altera_merlin_arbitrator#  Loading rsp_xbar_mux.altera_merlin_arb_adder#  Loading jtag_phy_embedded_in_jtag_master.altera_jtag_dc_streaming#  Loading altera_mf_ver.altera_std_synchronizer#  Loading jtag_phy_embedded_in_jtag_master.altera_jtag_streaming#  Loading jtag_phy_embedded_in_jtag_master.altera_jtag_sld_node#  Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_idle_remover#  Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_idle_inserter#  Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_clock_crosser#  Loading jtag_phy_embedded_in_jtag_master.altera_jtag_src_crosser#  Loading jtag_phy_embedded_in_jtag_master.altera_jtag_control_signal_crosser#  Loading transacto.packets_to_master#  Loading rst_controller.altera_reset_synchronizer#  Loading jtag_phy_embedded_in_jtag_master.altera_avalon_st_pipeline_base#  ** Warning: (vsim-8311) System Verilog assertions are supported only in Questasim.#  #  ** Error: (vsim-3063) C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(86): Port 'led_export' not found in the connected module (3rd connection).#  #          Region: /qsys_system_bfm_master_tb/dut#  ** Error: (vsim-3063) C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(86): Port 'button_export' not found in the connected module (4th connection).#  #          Region: /qsys_system_bfm_master_tb/dut#  ** Error: (vsim-3063) C:/Users/rm231795/Documents/work/JTAG/cellule/quartus/jtag_to_avalon_mm_tutorial/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv(86): Port 'resetrequest_reset' not found in the connected module (5th connection).#  #          Region: /qsys_system_bfm_master_tb/dut#  Error loading design

When trying to compile a simple verilog fulladder, Modelsim is ok. Isn't it showing a verilog license is available?

So what is your problem? The error message is pretty clear. The port names for the Qsys system in the BFM do not match the Qsys port names. Did you try looking into that?

The tutorial was written for a specific version of Quartus, and the port names in the error message are the port names generated by the Qsys version I used to create the tutorial. Since you have used a newer version of Qsys, then its likely the port name generation logic has changed (blame Altera, not me!). Qsys can be used to generate an example top-level HDL instance. If you do that, you will see that the port names have changed slightly, or that you have mistyped a name, either way, all you need to do is edit the HDL in the testbench to match the port names in the Qsys generated top-level, and your simulation will work fine.

Don't give up, you're almost there! :)

Cheers,

Dave

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(blame Altera, not me!)

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I certainly don't blame you! You spend time helping people like me and explaining why some errors happen so we can correct it easily next time. I would be mad to blame you!

Sorry if it's an easy thing to correct, I'll look at it tomorrow...

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Sorry if it's an easy thing to correct, I'll look at it tomorrow...

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It should be easy to correct. In the Qsys GUI click on the option "Generate HDL Example" (depending on Qsys version, its a tab or a "Generate" menu option).

Compare the Verilog module definition to the one used in the code. Correct the port names, and re-run the simulation script and it will work fine.

Cheers,

Dave

Right, I understood the error more clearly. OK for the ports names that are not the same but where?

I've seen the HDL example but I don't know what file I have to change.

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Right, I understood the error more clearly. OK for the ports names that are not the same but where?

I've seen the HDL example but I don't know what file I have to change.

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This is why errors are good. You're forced to read the code and understand :)

Given that you're trying to run qsys_system_bfm_master_tb, wouldn't you think that would be the place to start looking?

In the posts above this one, you state the path to that file, i.e., $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

If you look at that file, you should see the qsys_system instantiated. If the port names have changed in the generated qsys_instance (as shown by "Generate HDL Example"), then change the instance port names to match (you can leave the design-level signal names that connect to the ports the same) and the design should work.

Cheers,

Dave

Everything is corrected and it runs as specified in the tutorial!

The thing is I don't know what difference it will make for my project. First there would be many files to write and then I use VHDL so I have to translate everything from verilog (a language I don't know well). And what to look at?

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Everything is corrected and it runs as specified in the tutorial!

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Great.

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The thing is I don't know what difference it will make for my project.

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You should create your data capture logic, and simulate it, eg., create an Avalon-MM slave and then simulate it using the BFM.

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First there would be many files to write and then I use VHDL so I have to translate everything from verilog (a language I don't know well). And what to look at?

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I also use VHDL. The Altera BFM can be used with either language. I also use Modelsim-SE which supports both Verilog and VHDL at the same time.

The point of this exercise was to get you to look at a simulation. You may think its "hard", but its a critical part of designing with FPGAs. If you cannot take the time to learn the tools, then you will not succeed with your design.

Cheers,

Dave

Yes I will take the time to learn but I don't understand everything.

Please tell me what a BFM is exactly. And tell me what I should do (generate VHDL simulation files, create a simulation environment, look with Signaltap at what the stimulus should be...)