Data from FPGA to host

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Right, I understood the error more clearly. OK for the ports names that are not the same but where?

I've seen the HDL example but I don't know what file I have to change.

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This is why errors are good. You're forced to read the code and understand :)

Given that you're trying to run qsys_system_bfm_master_tb, wouldn't you think that would be the place to start looking?

In the posts above this one, you state the path to that file, i.e., $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

If you look at that file, you should see the qsys_system instantiated. If the port names have changed in the generated qsys_instance (as shown by "Generate HDL Example"), then change the instance port names to match (you can leave the design-level signal names that connect to the ports the same) and the design should work.

Cheers,

Dave