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Everything is corrected and it runs as specified in the tutorial!
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Great.
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The thing is I don't know what difference it will make for my project.
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You should create your data capture logic, and simulate it, eg., create an Avalon-MM slave and then simulate it using the BFM.
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First there would be many files to write and then I use VHDL so I have to translate everything from verilog (a language I don't know well). And what to look at?
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I also use VHDL. The Altera BFM can be used with either language. I also use Modelsim-SE which supports both Verilog and VHDL at the same time.
The point of this exercise was to get you to look at a simulation. You may think its "hard", but its a critical part of designing with FPGAs. If you cannot take the time to learn the tools, then you will not succeed with your design.
Cheers,
Dave
Honored Contributor
