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Altera_Forum
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11 years ago

Data from FPGA to host

Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Sorry if it's an easy thing to correct, I'll look at it tomorrow...

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It should be easy to correct. In the Qsys GUI click on the option "Generate HDL Example" (depending on Qsys version, its a tab or a "Generate" menu option).

Compare the Verilog module definition to the one used in the code. Correct the port names, and re-run the simulation script and it will work fine.

Cheers,

Dave