Data from FPGA to host

So what is your problem? The error message is pretty clear. The port names for the Qsys system in the BFM do not match the Qsys port names. Did you try looking into that?

The tutorial was written for a specific version of Quartus, and the port names in the error message are the port names generated by the Qsys version I used to create the tutorial. Since you have used a newer version of Qsys, then its likely the port name generation logic has changed (blame Altera, not me!). Qsys can be used to generate an example top-level HDL instance. If you do that, you will see that the port names have changed slightly, or that you have mistyped a name, either way, all you need to do is edit the HDL in the testbench to match the port names in the Qsys generated top-level, and your simulation will work fine.

Don't give up, you're almost there! :)

Cheers,

Dave