Data from FPGA to host

OK, I still have simulation problems but I know why (I think). I'll repair that and continue...

Tell me something I don't know: what need are the constraints? I see that Quartus II is complaining when I don't do that part but why? For me, doing things without any constraint is easier but it wants to be constrained!

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Tell me something I don't know: what need are the constraints? I see that Quartus II is complaining when I don't do that part but why? For me, doing things without any constraint is easier but it wants to be constrained!

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An FPGA design typically requires; HDL code to describe the design, FPGA device and device settings (eg, what to do with unused pins), pinout constraints, and timing constraints.

The first two things are absolutely required. The timing constraints are not required to synthesize a design, but Quartus will complain, because it recognizes that you are using synchronous logic (clocks), but it has no idea how what clock frequency you expect your design to operate at. That is why you have to provide timing constraints.

Cheers,

Dave

Here is my problem of the day:

I'm using SignalTap II with three signal. The first one is acting as the clock and the others are represented on this image:

https://www.alteraforum.com/forum/attachment.php?attachmentid=10256

ext_s0 is acting as the trigger on either edge so I would think it's constant before 0 but it's not. Can you explain?

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ext_s0 is acting as the trigger on either edge so I would think it's constant before 0 but it's not. Can you explain?

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Have you ever used an oscilloscope? When you trigger on a clock-like signal, the edge that the oscilloscope triggers on is not the "first edge" of the clock it is "an edge". The same is happening in your SignalTap II trace. When you arm the trigger, it captures the first edge after the arm command ...

Cheers,

Dave

OK for your explanation.

I was hoping the data to be recorded in a file I could get and give to my host program but I need the whole process so it doesn't seem a good idea...

I tried to begin the process 15 minutes after the start of the acquisition. This way I was pretty sure the trigger was armed and the first edge would be captured but it's not, I can still see activity before 0.

Now SignalTap II is giving a trace, what should I do to write all the process in the sdram (it's the finality I want to obtain)?

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what should I do to write all the process in the sdram (it's the finality I want to obtain)?

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Its a bit difficult to comment on this, as I don't really understand what you are trying to do.

As I commented earlier, you should be using simulation to test your design, and use SignalTap II to determine real-world stimulus for your simulation.

If you have not created a simulation of your system, you're making your life more difficult than it needs to be.

Create a simulation, create stimulus, and then try to make the simulation match your real world signals.

Cheers,

Dave

As I said, an external design is computing 4 signals, they are inputs on my de0-nano's GPIOs and one of them is acting as an external clock. I want to record all what happens during a certain process. I want this process to be analysed by a program (a C one) on the host computer.

I made a design that could record it in the SRAM but this memory was not large enough so I thought of writing in the SDRAM and that's where I'm stuck because I don't know how to work it.

For a real simulation I would have to know how to simulate a Qsys design and the program running on the Nios but it seems complicated for me.

I've done the SignalTap part but it doesn't seem useful if I can't simulate my design, right?

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As I said, an external design is computing 4 signals, they are inputs on my de0-nano's GPIOs and one of them is acting as an external clock.

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Ok. This sounds pretty simple. I'm not sure why you cannot trigger SignalTap II correctly then. I've had plenty of setups where I want to capture the "first" transition on a signal and it worked fine, eg., even at power-on using the power-on trigger feature within SignalTap II.

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I want to record all what happens during a certain process. I want this process to be analysed by a program (a C one) on the host computer.

I made a design that could record it in the SRAM but this memory was not large enough so I thought of writing in the SDRAM and that's where I'm stuck because I don't know how to work it.

For a real simulation I would have to know how to simulate a Qsys design and the program running on the Nios but it seems complicated for me.

I've done the SignalTap part but it doesn't seem useful if I can't simulate my design, right?

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Everything is complicated until you've figured out how to do it :)

Did you simulate your simpler SRAM design? You should be able to simulate data capture into SRAM, then synthesize it, and check that it works ok in hardware. Once you've convinced yourself that works, you could go onto using the SDRAM for longer data capture, and then skip simulating that more complicated system if you think you need to.

Personally, I simulate everything until I understand what needs to happen, and then the hardware "just works".

How did I learn to use the simulator? I spent time learning how to use it. You'll need to do the same.

Cheers,

Dave

I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it?

For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.